{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9633690","patent":{"patent_number":"US-9633690","title":"Cycle-slip resilient iterative data storage read channel architecture","assignee":null,"inventors":[],"filing_date":"2015-11-02T00:00:00.000Z","publication_date":"2017-04-25T00:00:00.000Z","cpc_codes":["G11B","G11B","G11B","G11B"],"num_claims":20,"abstract":"In one embodiment, a system for cycle-slip resilient iterative read channel operation includes a processor and logic integrated with and/or executable by the processor. The logic is configured to, in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced, execute cycle-slip detection on signal samples to detect one or more cycle-slip events. Also, the logic is configured to selectively alter a timing estimate driving a phase-locked loop (PLL) during any time interval determined to experience a cycle slip in a first pass as indicated by one or more cycle-slip pointers. Additionally, the logic is configured to generate a set of decisions provided by a detector and generate a set of decisions provided by a decoder. Moreover, the logic is configured to output decoding information relating to the signal samples in response to a decoding algorithm producing a valid codeword."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cycle-slip resilient iterative data storage read channel architecture","description":"In one embodiment, a system for cycle-slip resilient iterative read channel operation includes a processor and logic integrated with and/or executable by the processor. The logic is configured to, in ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9633690","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9633690","citation_suggestion":"Patentable. \"Cycle-slip resilient iterative data storage read channel architecture\" (US-9633690). https://patentable.app/patents/US-9633690","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9633690","json":"https://patentable.app/api/llm-context/US-9633690","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T17:45:40.582Z"}