{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9633703","patent":{"patent_number":"US-9633703","title":"Semiconductor memory sensing architecture","assignee":null,"inventors":[],"filing_date":"2016-06-21T00:00:00.000Z","publication_date":"2017-04-25T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":15,"abstract":"A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated. The circuit arrangement further has a latch connected to an output of the sense amplifier, the latch capturing the output from the sense amplifier when the sense amplifier determines the logic state of the selected memory cell and sending a signal to the sense amplifier to disable itself."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory sensing architecture","description":"A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9633703","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9633703","citation_suggestion":"Patentable. \"Semiconductor memory sensing architecture\" (US-9633703). https://patentable.app/patents/US-9633703","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9633703","json":"https://patentable.app/api/llm-context/US-9633703","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:40:13.142Z"}