{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9633909","patent":{"patent_number":"US-9633909","title":"Process for integrated circuit fabrication including a liner silicide with low contact resistance","assignee":null,"inventors":[],"filing_date":"2015-11-16T00:00:00.000Z","publication_date":"2017-04-25T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":42,"abstract":"An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Process for integrated circuit fabrication including a liner silicide with low contact resistance","description":"An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain re","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9633909","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9633909","citation_suggestion":"Patentable. \"Process for integrated circuit fabrication including a liner silicide with low contact resistance\" (US-9633909). https://patentable.app/patents/US-9633909","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9633909","json":"https://patentable.app/api/llm-context/US-9633909","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:55:47.625Z"}