{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9639488","patent":{"patent_number":"US-9639488","title":"Encoding valid data states in source synchronous bus interfaces using clock signal transitions","assignee":null,"inventors":[],"filing_date":"2014-06-20T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","H04L"],"num_claims":18,"abstract":"Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Encoding valid data states in source synchronous bus interfaces using clock signal transitions","description":"Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, on","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9639488","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9639488","citation_suggestion":"Patentable. \"Encoding valid data states in source synchronous bus interfaces using clock signal transitions\" (US-9639488). https://patentable.app/patents/US-9639488","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9639488","json":"https://patentable.app/api/llm-context/US-9639488","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:14:52.777Z"}