{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9639641","patent":{"patent_number":"US-9639641","title":"Method and system for functional verification and power analysis of clock-gated integrated circuits","assignee":null,"inventors":[],"filing_date":"2015-08-20T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"An apparatus for monitoring operation of a design under test (DUT) comprises a plurality of inputs comprising: an incoming clock edge input connected to detect active clock edges provided to a monitored clock gate; an outgoing clock edge input connected to detect active clock edges sent from the monitored clock gate; an enable input connected to detect enable signals provided to the monitored clock gate and any leaf clock gates connected to receive clock edges through the monitored clock gate; and a protocol input connected to receive protocol signals specifying when the monitored clock gate is required to output active clock edges. The apparatus also comprises a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine protocol compliance and to calculate energy consequences of dropping of active clock edges."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for functional verification and power analysis of clock-gated integrated circuits","description":"An apparatus for monitoring operation of a design under test (DUT) comprises a plurality of inputs comprising: an incoming clock edge input connected to detect active clock edges provided to a monitor","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9639641","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9639641","citation_suggestion":"Patentable. \"Method and system for functional verification and power analysis of clock-gated integrated circuits\" (US-9639641). https://patentable.app/patents/US-9639641","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9639641","json":"https://patentable.app/api/llm-context/US-9639641","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:38:03.184Z"}