{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9640229","patent":{"patent_number":"US-9640229","title":"Memory circuit and layout structure of a memory circuit","assignee":null,"inventors":[],"filing_date":"2015-04-21T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":15,"abstract":"A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory circuit and layout structure of a memory circuit","description":"A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is inc","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9640229","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9640229","citation_suggestion":"Patentable. \"Memory circuit and layout structure of a memory circuit\" (US-9640229). https://patentable.app/patents/US-9640229","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9640229","json":"https://patentable.app/api/llm-context/US-9640229","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:20:02.148Z"}