{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9640236","patent":{"patent_number":"US-9640236","title":"Reduced load memory module using wire bonds and a plurality of rank signals","assignee":null,"inventors":[],"filing_date":"2015-03-12T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","H01L","H01L"],"num_claims":17,"abstract":"An apparatus for reducing load in a memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reduced load memory module using wire bonds and a plurality of rank signals","description":"An apparatus for reducing load in a memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9640236","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9640236","citation_suggestion":"Patentable. \"Reduced load memory module using wire bonds and a plurality of rank signals\" (US-9640236). https://patentable.app/patents/US-9640236","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9640236","json":"https://patentable.app/api/llm-context/US-9640236","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:40:03.802Z"}