{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9640280","patent":{"patent_number":"US-9640280","title":"Power domain aware insertion methods and designs for testing and repairing memory","assignee":null,"inventors":[],"filing_date":"2015-11-02T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C"],"num_claims":20,"abstract":"Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power domain aware insertion methods and designs for testing and repairing memory","description":"Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9640280","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9640280","citation_suggestion":"Patentable. \"Power domain aware insertion methods and designs for testing and repairing memory\" (US-9640280). https://patentable.app/patents/US-9640280","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9640280","json":"https://patentable.app/api/llm-context/US-9640280","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:03:44.002Z"}