{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9640535","patent":{"patent_number":"US-9640535","title":"Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices","assignee":null,"inventors":[],"filing_date":"2016-06-07T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. An etch stop layer is positioned above and covers a portion of the active region, an interlayer dielectric material is positioned above the active region and covers the etch stop layer, and a confined raised source/drain region is positioned on and in contact with an upper surface of the active region. The confined raised source/drain region extends laterally between and contacts a lower sidewall surface portion of the sidewall spacer and at least a portion of a sidewall surface of the etch stop layer, and a conductive contact element extends through the interlayer dielectric material and directly contacts an upper surface of the confined raised source/drain region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices","description":"A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positio","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9640535","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9640535","citation_suggestion":"Patentable. \"Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices\" (US-9640535). https://patentable.app/patents/US-9640535","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9640535","json":"https://patentable.app/api/llm-context/US-9640535","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:57:17.778Z"}