{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9640605","patent":{"patent_number":"US-9640605","title":"Semiconductor device, layout design and method for manufacturing a semiconductor device","assignee":null,"inventors":[],"filing_date":"2015-04-23T00:00:00.000Z","publication_date":"2017-05-02T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device, layout design and method for manufacturing a semiconductor device","description":"A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9640605","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9640605","citation_suggestion":"Patentable. \"Semiconductor device, layout design and method for manufacturing a semiconductor device\" (US-9640605). https://patentable.app/patents/US-9640605","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9640605","json":"https://patentable.app/api/llm-context/US-9640605","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:23:20.261Z"}