{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9645963","patent":{"patent_number":"US-9645963","title":"Systems and methods for concurrently testing master and slave devices in a system on a chip","assignee":null,"inventors":[],"filing_date":"2015-02-16T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":19,"abstract":"An integrated circuit includes a substrate, a master system on the substrate, a slave system on the substrate that is coupled to communicate with the master system, a first clock signal coupled to the master system, and a second clock signal coupled to the slave system. The master system is configured to isolate the slave system from the master system while a first test of the master system is conducted in parallel with a second test of the slave system. The master system uses the first clock signal during the first test and the slave system uses the second clock signal during the second test."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Systems and methods for concurrently testing master and slave devices in a system on a chip","description":"An integrated circuit includes a substrate, a master system on the substrate, a slave system on the substrate that is coupled to communicate with the master system, a first clock signal coupled to the","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9645963","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9645963","citation_suggestion":"Patentable. \"Systems and methods for concurrently testing master and slave devices in a system on a chip\" (US-9645963). https://patentable.app/patents/US-9645963","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9645963","json":"https://patentable.app/api/llm-context/US-9645963","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:35:02.354Z"}