{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9646120","patent":{"patent_number":"US-9646120","title":"Method and system for trace compaction during emulation of a circuit design","assignee":null,"inventors":[],"filing_date":"2016-05-19T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":6,"abstract":"The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for trace compaction during emulation of a circuit design","description":"The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compact","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9646120","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9646120","citation_suggestion":"Patentable. \"Method and system for trace compaction during emulation of a circuit design\" (US-9646120). https://patentable.app/patents/US-9646120","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9646120","json":"https://patentable.app/api/llm-context/US-9646120","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T13:37:05.745Z"}