{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9646123","patent":{"patent_number":"US-9646123","title":"Standard cell design with reduced cell delay","assignee":null,"inventors":[],"filing_date":"2014-12-31T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a first node. The standard cell further includes a first NMOS transistor and a third NMOS transistor whose gate terminal respectively receive the first input and the second input. A drain terminal of each of the first NMOS transistor and the third NMOS transistor is coupled to the first node. The first NMOS transistor is coupled to a second NMOS transistor, and the third NMOS transistor is coupled to a fourth NMOS transistor. A gate terminal of the second NMOS transistor and the fourth NMOS transistor respectively receives the second input and the first input."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Standard cell design with reduced cell delay","description":"The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A d","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9646123","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9646123","citation_suggestion":"Patentable. \"Standard cell design with reduced cell delay\" (US-9646123). https://patentable.app/patents/US-9646123","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9646123","json":"https://patentable.app/api/llm-context/US-9646123","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:40:57.101Z"}