{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9646836","patent":{"patent_number":"US-9646836","title":"Semiconductor device manufacturing method","assignee":null,"inventors":[],"filing_date":"2015-05-22T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":18,"abstract":"Provided is a semiconductor device manufacturing method such that miniaturization of a parallel p-n layer can be achieved, and on-state resistance can be reduced. Firstly, deposition of an n−-type epitaxial layer, and formation of an n-type impurity region and p-type impurity region that form an n-type region and p-type region of a parallel p-n layer, are repeatedly carried out. Furthermore, an n−-type counter region is formed in the vicinity of the p-type impurity region in the uppermost n−-type epitaxial layer forming the parallel p-n layer. Next, an n−-type epitaxial layer is deposited on the n−-type epitaxial layer. Next, a MOS gate structure is formed in the n−-type epitaxial layer. At this time, when carrying out a p-type base region diffusion process, the n-type and p-type impurity regions are caused to diffuse, thereby forming the n-type region and p-type region of the parallel p-n layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device manufacturing method","description":"Provided is a semiconductor device manufacturing method such that miniaturization of a parallel p-n layer can be achieved, and on-state resistance can be reduced. Firstly, deposition of an n−-type epi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9646836","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9646836","citation_suggestion":"Patentable. \"Semiconductor device manufacturing method\" (US-9646836). https://patentable.app/patents/US-9646836","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9646836","json":"https://patentable.app/api/llm-context/US-9646836","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:33:57.111Z"}