{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9646888","patent":{"patent_number":"US-9646888","title":"Technique of reducing shallow trench isolation loss during fin formation in finFETs","assignee":null,"inventors":[],"filing_date":"2016-01-08T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":9,"abstract":"A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer, etching to the semiconductor substrate to form a fin-type structure and a groove; forming an isolation material layer in the regions between adjacent fins of the fin-type structure and in the groove; removing a portion of the isolation material layer that is located above the hard mask layer to form a shallow trench isolation; and forming a second mask layer over the hard mask layer, the second mask layer having an opening above the shallow trench isolation; performing ion implantation to the shallow trench isolation through the opening; removing the second mask layer and the hard mask layer; and removing a portion of the isolation material layer located in the regions between adjacent fins of the fin-type structure and a portion of the shallow trench isolation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Technique of reducing shallow trench isolation loss during fin formation in finFETs","description":"A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer, etching to the semiconductor substrate ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9646888","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9646888","citation_suggestion":"Patentable. \"Technique of reducing shallow trench isolation loss during fin formation in finFETs\" (US-9646888). https://patentable.app/patents/US-9646888","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9646888","json":"https://patentable.app/api/llm-context/US-9646888","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:15:16.973Z"}