{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9646932","patent":{"patent_number":"US-9646932","title":"Method for forming interconnect structure that avoids via recess","assignee":null,"inventors":[],"filing_date":"2016-02-01T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for forming interconnect structure that avoids via recess","description":"A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9646932","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9646932","citation_suggestion":"Patentable. \"Method for forming interconnect structure that avoids via recess\" (US-9646932). https://patentable.app/patents/US-9646932","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9646932","json":"https://patentable.app/api/llm-context/US-9646932","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:17:31.620Z"}