{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9647078","patent":{"patent_number":"US-9647078","title":"Closed cell configuration to increase channel density for sub-micron planar semiconductor power device","assignee":null,"inventors":[],"filing_date":"2015-08-28T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":10,"abstract":"A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Closed cell configuration to increase channel density for sub-micron planar semiconductor power device","description":"A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9647078","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9647078","citation_suggestion":"Patentable. \"Closed cell configuration to increase channel density for sub-micron planar semiconductor power device\" (US-9647078). https://patentable.app/patents/US-9647078","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9647078","json":"https://patentable.app/api/llm-context/US-9647078","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:04:46.111Z"}