{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9647107","patent":{"patent_number":"US-9647107","title":"Fabrication method for forming vertical transistor on hemispherical or polygonal patterned semiconductor substrate","assignee":null,"inventors":[],"filing_date":"2016-01-22T00:00:00.000Z","publication_date":"2017-05-09T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":4,"abstract":"A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Fabrication method for forming vertical transistor on hemispherical or polygonal patterned semiconductor substrate","description":"A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this dri","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9647107","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9647107","citation_suggestion":"Patentable. \"Fabrication method for forming vertical transistor on hemispherical or polygonal patterned semiconductor substrate\" (US-9647107). https://patentable.app/patents/US-9647107","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9647107","json":"https://patentable.app/api/llm-context/US-9647107","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:20:10.949Z"}