{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9651617","patent":{"patent_number":"US-9651617","title":"Full address coverage during memory array built-in self test with minimum transitions","assignee":null,"inventors":[],"filing_date":"2015-09-25T00:00:00.000Z","publication_date":"2017-05-16T00:00:00.000Z","cpc_codes":["G06F","G11C","G11C"],"num_claims":20,"abstract":"Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Full address coverage during memory array built-in self test with minimum transitions","description":"Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9651617","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9651617","citation_suggestion":"Patentable. \"Full address coverage during memory array built-in self test with minimum transitions\" (US-9651617). https://patentable.app/patents/US-9651617","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9651617","json":"https://patentable.app/api/llm-context/US-9651617","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:15:14.001Z"}