{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9652246","patent":{"patent_number":"US-9652246","title":"Banked physical register data flow architecture in out-of-order processors","assignee":null,"inventors":[],"filing_date":"2013-12-20T00:00:00.000Z","publication_date":"2017-05-16T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"In a method of executing instructions in a processing system, respective global age tags are assigned to each of the one or more instructions fetched for processing by the processing system. Each global age tag indicates an age of the corresponding instruction in the processing system. Respective physical registers in a physical register file are allocated to each destination logical register referenced by each instruction. The respective global age tags are written to the in respective physical registers allocated to the destination logical registers of the instructions. The instructions are executed by the processing system. At least some of the instructions are executed in an order different from a program order of the instructions."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Banked physical register data flow architecture in out-of-order processors","description":"In a method of executing instructions in a processing system, respective global age tags are assigned to each of the one or more instructions fetched for processing by the processing system. Each glob","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9652246","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9652246","citation_suggestion":"Patentable. \"Banked physical register data flow architecture in out-of-order processors\" (US-9652246). https://patentable.app/patents/US-9652246","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9652246","json":"https://patentable.app/api/llm-context/US-9652246","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T14:41:11.799Z"}