{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9652560","patent":{"patent_number":"US-9652560","title":"Non-blocking memory management unit","assignee":null,"inventors":[],"filing_date":"2011-12-07T00:00:00.000Z","publication_date":"2017-05-16T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":17,"abstract":"Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce the chances that a page fault will result in a GPU-pipeline stall. In one embodiment, a processor includes a graphics processor pipeline and a memory management unit. The graphics processor pipeline includes a plurality of pipeline stages. The memory management unit is configured to determine that a first data request from a first of the plurality of pipeline stages causes a page fault, and to service requests from one or more others of the plurality of pipeline stages while the page fault is being serviced."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Non-blocking memory management unit","description":"Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9652560","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9652560","citation_suggestion":"Patentable. \"Non-blocking memory management unit\" (US-9652560). https://patentable.app/patents/US-9652560","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9652560","json":"https://patentable.app/api/llm-context/US-9652560","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:20:08.799Z"}