{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9653161","patent":{"patent_number":"US-9653161","title":"Tamper-resistant non-volatile memory device comprising an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, a read circuit that, in operation, selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, and a write circuit that, in operation, performs a write operation corresponding to one of the two values among memory cells","assignee":null,"inventors":[],"filing_date":"2015-11-11T00:00:00.000Z","publication_date":"2017-05-16T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":13,"abstract":"A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Tamper-resistant non-volatile memory device comprising an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, a read circuit that, in operation, selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, and a write circuit that, in operation, performs a write operation corresponding to one of the two values among memory cells","description":"A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operati","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9653161","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9653161","citation_suggestion":"Patentable. \"Tamper-resistant non-volatile memory device comprising an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, a read circuit that, in operation, selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, and a write circuit that, in operation, performs a write operation corresponding to one of the two values among memory cells\" (US-9653161). https://patentable.app/patents/US-9653161","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9653161","json":"https://patentable.app/api/llm-context/US-9653161","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:19:56.339Z"}