{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9653164","patent":{"patent_number":"US-9653164","title":"Method for integrating non-volatile memory cells with static random access memory cells and logic transistors","assignee":null,"inventors":[],"filing_date":"2015-03-13T00:00:00.000Z","publication_date":"2017-05-16T00:00:00.000Z","cpc_codes":["G11C","H01L"],"num_claims":17,"abstract":"A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for integrating non-volatile memory cells with static random access memory cells and logic transistors","description":"A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coati","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9653164","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9653164","citation_suggestion":"Patentable. \"Method for integrating non-volatile memory cells with static random access memory cells and logic transistors\" (US-9653164). https://patentable.app/patents/US-9653164","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9653164","json":"https://patentable.app/api/llm-context/US-9653164","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:03:07.529Z"}