{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9653372","patent":{"patent_number":"US-9653372","title":"Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby","assignee":null,"inventors":[],"filing_date":"2015-08-12T00:00:00.000Z","publication_date":"2017-05-16T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":18,"abstract":"A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first semiconductor chip and the dummy substrate, removing the dummy substrate to expose the first semiconductor chip, disposing a second semiconductor chip on the exposed first semiconductor chip, forming an insulating layer on the second semiconductor chip, the first semiconductor chip, and the mold substrate, and forming a plurality of redistribution lines that electrically connects the first semiconductor chip and the second semiconductor chip through the insulating layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby","description":"A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first semiconductor chip and the dummy substr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9653372","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9653372","citation_suggestion":"Patentable. \"Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby\" (US-9653372). https://patentable.app/patents/US-9653372","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9653372","json":"https://patentable.app/api/llm-context/US-9653372","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:02:49.040Z"}