{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9658675","patent":{"patent_number":"US-9658675","title":"Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores","assignee":null,"inventors":[],"filing_date":"2015-02-19T00:00:00.000Z","publication_date":"2017-05-23T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":24,"abstract":"Subject matter disclosed herein relates to arrangements and techniques that provide for sending messages among processing nodes over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores and co-processors. The processing cores and co-processors are coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. If a processing core or co-processor needs to send a message and the corresponding first buffer is full, if the message includes a flag that indicates a WAIT function, then the processing core and/or co-processor enters a low power state until the first buffer is available; otherwise the message is ignored and not sent. Additionally, if a second buffer is empty, then the corresponding processing core and/or co-processor enters the low power state."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores","description":"Subject matter disclosed herein relates to arrangements and techniques that provide for sending messages among processing nodes over a network-on-chip (NoC). More particularly, the present disclosure ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9658675","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9658675","citation_suggestion":"Patentable. \"Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores\" (US-9658675). https://patentable.app/patents/US-9658675","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9658675","json":"https://patentable.app/api/llm-context/US-9658675","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:26:20.476Z"}