{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9658853","patent":{"patent_number":"US-9658853","title":"Techniques for increasing instruction issue rate and reducing latency in an out-of order processor","assignee":null,"inventors":[],"filing_date":"2014-07-31T00:00:00.000Z","publication_date":"2017-05-23T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":19,"abstract":"A technique for operating a processor includes storing a first result to a writeback buffer, in response to a first execution unit of the processor attempting to write the first result of a first completed instruction to a register file of the processor at a same processor time as a second execution unit of the processor is attempting to write a second result of a second completed instruction to the register file. The writeback buffer is positioned in a dataflow between the first execution unit and the register file. A buffer full indicator logic is used to detect that the writeback buffer is unavailable. A buffer unavailable signal is transmitted, from the buffer full indicator logic, in response to detecting the writeback buffer is unavailable. In response to receiving the buffer unavailable signal, a buffer retrieving logic writes the first result from the writeback buffer to the register file."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Techniques for increasing instruction issue rate and reducing latency in an out-of order processor","description":"A technique for operating a processor includes storing a first result to a writeback buffer, in response to a first execution unit of the processor attempting to write the first result of a first comp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9658853","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9658853","citation_suggestion":"Patentable. \"Techniques for increasing instruction issue rate and reducing latency in an out-of order processor\" (US-9658853). https://patentable.app/patents/US-9658853","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9658853","json":"https://patentable.app/api/llm-context/US-9658853","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:39:07.636Z"}