{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9659133","patent":{"patent_number":"US-9659133","title":"Method, system and computer program product for generating layout for semiconductor device","assignee":null,"inventors":[],"filing_date":"2013-10-17T00:00:00.000Z","publication_date":"2017-05-23T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":20,"abstract":"A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method, system and computer program product for generating layout for semiconductor device","description":"A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements ha","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9659133","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9659133","citation_suggestion":"Patentable. \"Method, system and computer program product for generating layout for semiconductor device\" (US-9659133). https://patentable.app/patents/US-9659133","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9659133","json":"https://patentable.app/api/llm-context/US-9659133","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:15:49.510Z"}