{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9665466","patent":{"patent_number":"US-9665466","title":"Debug architecture for multithreaded processors","assignee":null,"inventors":[],"filing_date":"2014-09-02T00:00:00.000Z","publication_date":"2017-05-30T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":19,"abstract":"Debug architecture for multithreaded processors. In some embodiments, a method includes, in response to receiving a halt command, saving a context of a thread being executed by a processor core to a context memory distinct from the processor core; suspending execution of the thread; and initiating a debug of the thread using the context stored in the context memory. In other embodiments, an integrated circuit includes a processor core; a context management circuit coupled to the core; and a debug support circuit coupled to the context management circuit, the debug support circuit configured to send a halt request to the context management circuit and the context management circuit configured to, in response to having received the request, facilitate a debug operation by causing execution of a thread running on the core to be suspended and saving a context of the thread into a context memory distinct from the core."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Debug architecture for multithreaded processors","description":"Debug architecture for multithreaded processors. In some embodiments, a method includes, in response to receiving a halt command, saving a context of a thread being executed by a processor core to a c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9665466","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9665466","citation_suggestion":"Patentable. \"Debug architecture for multithreaded processors\" (US-9665466). https://patentable.app/patents/US-9665466","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9665466","json":"https://patentable.app/api/llm-context/US-9665466","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:41:21.383Z"}