{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9665490","patent":{"patent_number":"US-9665490","title":"Apparatus and method for repairing cache arrays in a multi-core microprocessor","assignee":null,"inventors":[],"filing_date":"2014-05-22T00:00:00.000Z","publication_date":"2017-05-30T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G11C","G06F","G06F","G11C"],"num_claims":21,"abstract":"An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configuration data sets. One of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store the decompressed configuration data sets for one or more cache memories in the stores. Each of the plurality of cores includes reset logic and sleep logic. The reset logic is configured to employ the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic is configured to determine that power is restored following a power gating event, and is configured to subsequently access the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and method for repairing cache arrays in a multi-core microprocessor","description":"An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configurat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9665490","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9665490","citation_suggestion":"Patentable. \"Apparatus and method for repairing cache arrays in a multi-core microprocessor\" (US-9665490). https://patentable.app/patents/US-9665490","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9665490","json":"https://patentable.app/api/llm-context/US-9665490","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:37:35.951Z"}