{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9665509","patent":{"patent_number":"US-9665509","title":"Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system","assignee":null,"inventors":[],"filing_date":"2014-08-20T00:00:00.000Z","publication_date":"2017-05-30T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":22,"abstract":"Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system","description":"Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9665509","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9665509","citation_suggestion":"Patentable. \"Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system\" (US-9665509). https://patentable.app/patents/US-9665509","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9665509","json":"https://patentable.app/api/llm-context/US-9665509","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:33:35.555Z"}