{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9666492","patent":{"patent_number":"US-9666492","title":"CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture","assignee":null,"inventors":[],"filing_date":"2015-07-13T00:00:00.000Z","publication_date":"2017-05-30T00:00:00.000Z","cpc_codes":["B82Y","H01L","H01L","H01L","H01L"],"num_claims":17,"abstract":"Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture","description":"Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In em","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9666492","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9666492","citation_suggestion":"Patentable. \"CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture\" (US-9666492). https://patentable.app/patents/US-9666492","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9666492","json":"https://patentable.app/api/llm-context/US-9666492","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T16:32:04.829Z"}