{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9671447","patent":{"patent_number":"US-9671447","title":"Method of analyzing error rate in system-on-chip","assignee":null,"inventors":[],"filing_date":"2014-12-30T00:00:00.000Z","publication_date":"2017-06-06T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":5,"abstract":"In order to improve reliability of a system-on-chip (SoC) through fault tolerance verification, there is provided a method of analyzing an error rate in a system-on-chip (SoC) having at least one internal block obtained by interconnecting two or more gates, comprising: applying an input signal to an input terminal of a certain internal block; defining an input error rate of each gate of the internal block; and defining an output error rate of the internal block based on the input error rate of each gate and an error rate propagating to an output terminal. As a result, there is proposed a method of analyzing a change of the output error rate depending on the input error rate in a gate level in error model development necessary to design and verify a fault-tolerant SoC. Therefore, it is possible to analyze errors in each gate and formularize error rate information modeling including an input/output relationship between each gate of a digital circuit in a library form."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of analyzing error rate in system-on-chip","description":"In order to improve reliability of a system-on-chip (SoC) through fault tolerance verification, there is provided a method of analyzing an error rate in a system-on-chip (SoC) having at least one inte","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9671447","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9671447","citation_suggestion":"Patentable. \"Method of analyzing error rate in system-on-chip\" (US-9671447). https://patentable.app/patents/US-9671447","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9671447","json":"https://patentable.app/api/llm-context/US-9671447","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:32:38.434Z"}