{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9672192","patent":{"patent_number":"US-9672192","title":"High performance implementation of the FFT butterfly computation","assignee":null,"inventors":[],"filing_date":"2015-11-11T00:00:00.000Z","publication_date":"2017-06-06T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":3,"abstract":"This invention is a FFT butterfly circuit. This circuit includes four temporary data registers connected to three memories. The three memories include read/write X and Y memories and a read only twiddle coefficient memory. A multiplier-accumulator forms a product and accumulates the product with one of two accumulator registers. A register file with plural registers is loaded from one of the accumulator registers or the fourth temporary data register. An adder/subtracter forms a selected one of a sum of registers or a difference of registers. A write buffer with two buffers temporarily stores data from the adder/subtracter before storage in the first or second memory. The X and Y memories must be read/write but the twiddle memory may be read only."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High performance implementation of the FFT butterfly computation","description":"This invention is a FFT butterfly circuit. This circuit includes four temporary data registers connected to three memories. The three memories include read/write X and Y memories and a read only twidd","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9672192","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9672192","citation_suggestion":"Patentable. \"High performance implementation of the FFT butterfly computation\" (US-9672192). https://patentable.app/patents/US-9672192","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9672192","json":"https://patentable.app/api/llm-context/US-9672192","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:19:22.907Z"}