{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9673050","patent":{"patent_number":"US-9673050","title":"Method of patterning incorporating overlay error protection","assignee":null,"inventors":[],"filing_date":"2015-09-24T00:00:00.000Z","publication_date":"2017-06-06T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":18,"abstract":"Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spacer to define a hard border between features to be patterned. Such a spacer is positioned underneath an overlying relief pattern so that a portion of the spacer is exposed and protecting an underlying layer. Techniques herein can be used for metallization, and, in particular, metallization of a first metal layer above electronic device contacts. More broadly, techniques herein can be used for any type of critical placement where one structure is extremely close to another structure, such as with sub-resolution dimensions."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of patterning incorporating overlay error protection","description":"Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spa","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9673050","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9673050","citation_suggestion":"Patentable. \"Method of patterning incorporating overlay error protection\" (US-9673050). https://patentable.app/patents/US-9673050","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9673050","json":"https://patentable.app/api/llm-context/US-9673050","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:21:55.607Z"}