{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9676619","patent":{"patent_number":"US-9676619","title":"Method for wafer-level chip scale package testing","assignee":null,"inventors":[],"filing_date":"2016-04-27T00:00:00.000Z","publication_date":"2017-06-13T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":18,"abstract":"The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for wafer-level chip scale package testing","description":"The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9676619","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9676619","citation_suggestion":"Patentable. \"Method for wafer-level chip scale package testing\" (US-9676619). https://patentable.app/patents/US-9676619","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9676619","json":"https://patentable.app/api/llm-context/US-9676619","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:42:38.255Z"}