{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9678872","patent":{"patent_number":"US-9678872","title":"Memory paging for processors using physical addresses","assignee":null,"inventors":[],"filing_date":"2015-01-16T00:00:00.000Z","publication_date":"2017-06-13T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G11C","G06F","G06F","G06F"],"num_claims":20,"abstract":"A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory paging for processors using physical addresses","description":"A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9678872","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9678872","citation_suggestion":"Patentable. \"Memory paging for processors using physical addresses\" (US-9678872). https://patentable.app/patents/US-9678872","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9678872","json":"https://patentable.app/api/llm-context/US-9678872","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:40:11.166Z"}