{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9679629","patent":{"patent_number":"US-9679629","title":"Memory device having wiring layout for electrically connecting to switch and capacitor components","assignee":null,"inventors":[],"filing_date":"2016-05-05T00:00:00.000Z","publication_date":"2017-06-13T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":18,"abstract":"Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device having wiring layout for electrically connecting to switch and capacitor components","description":"Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a f","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9679629","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9679629","citation_suggestion":"Patentable. \"Memory device having wiring layout for electrically connecting to switch and capacitor components\" (US-9679629). https://patentable.app/patents/US-9679629","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9679629","json":"https://patentable.app/api/llm-context/US-9679629","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:36:03.685Z"}