{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9679664","patent":{"patent_number":"US-9679664","title":"Method and system for providing a smart memory architecture","assignee":null,"inventors":[],"filing_date":"2013-07-05T00:00:00.000Z","publication_date":"2017-06-13T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G06F","G11C","G11C","G11C","G11C"],"num_claims":30,"abstract":"A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for providing a smart memory architecture","description":"A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller ca","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9679664","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9679664","citation_suggestion":"Patentable. \"Method and system for providing a smart memory architecture\" (US-9679664). https://patentable.app/patents/US-9679664","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9679664","json":"https://patentable.app/api/llm-context/US-9679664","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:37:34.445Z"}