{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9680490","patent":{"patent_number":"US-9680490","title":"Background calibration of interleaved timing errors in digital to analog converters","assignee":null,"inventors":[],"filing_date":"2016-08-17T00:00:00.000Z","publication_date":"2017-06-13T00:00:00.000Z","cpc_codes":["H04B","H04B"],"num_claims":6,"abstract":"System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Background calibration of interleaved timing errors in digital to analog converters","description":"System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9680490","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9680490","citation_suggestion":"Patentable. \"Background calibration of interleaved timing errors in digital to analog converters\" (US-9680490). https://patentable.app/patents/US-9680490","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9680490","json":"https://patentable.app/api/llm-context/US-9680490","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:38:07.838Z"}