{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9684360","patent":{"patent_number":"US-9684360","title":"Dynamically controlling power management of an on-die memory of a processor","assignee":null,"inventors":[],"filing_date":"2014-10-30T00:00:00.000Z","publication_date":"2017-06-20T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":16,"abstract":"In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Dynamically controlling power management of an on-die memory of a processor","description":"In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a pa","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9684360","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9684360","citation_suggestion":"Patentable. \"Dynamically controlling power management of an on-die memory of a processor\" (US-9684360). https://patentable.app/patents/US-9684360","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9684360","json":"https://patentable.app/api/llm-context/US-9684360","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:18:31.790Z"}