{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9684624","patent":{"patent_number":"US-9684624","title":"Receive clock calibration for a serial bus","assignee":null,"inventors":[],"filing_date":"2015-02-06T00:00:00.000Z","publication_date":"2017-06-20T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","H04L"],"num_claims":23,"abstract":"Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Receive clock calibration for a serial bus","description":"Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9684624","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9684624","citation_suggestion":"Patentable. \"Receive clock calibration for a serial bus\" (US-9684624). https://patentable.app/patents/US-9684624","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9684624","json":"https://patentable.app/api/llm-context/US-9684624","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:20:08.386Z"}