{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9684756","patent":{"patent_number":"US-9684756","title":"Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design","assignee":null,"inventors":[],"filing_date":"2016-01-25T00:00:00.000Z","publication_date":"2017-06-20T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","H01L","G06F","G06F","G06F","H04B"],"num_claims":1,"abstract":"Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design","description":"Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9684756","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9684756","citation_suggestion":"Patentable. \"Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design\" (US-9684756). https://patentable.app/patents/US-9684756","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9684756","json":"https://patentable.app/api/llm-context/US-9684756","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:39:24.678Z"}