{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9685141","patent":{"patent_number":"US-9685141","title":"MDLL/PLL hybrid design with uniformly distributed output phases","assignee":null,"inventors":[],"filing_date":"2015-01-09T00:00:00.000Z","publication_date":"2017-06-20T00:00:00.000Z","cpc_codes":["G09G","G09G","G09G"],"num_claims":21,"abstract":"A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"MDLL/PLL hybrid design with uniformly distributed output phases","description":"A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connect","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9685141","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9685141","citation_suggestion":"Patentable. \"MDLL/PLL hybrid design with uniformly distributed output phases\" (US-9685141). https://patentable.app/patents/US-9685141","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9685141","json":"https://patentable.app/api/llm-context/US-9685141","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:55:36.148Z"}