{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9685536","patent":{"patent_number":"US-9685536","title":"Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain","assignee":null,"inventors":[],"filing_date":"2012-02-29T00:00:00.000Z","publication_date":"2017-06-20T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":11,"abstract":"Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain","description":"Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The stru","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9685536","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9685536","citation_suggestion":"Patentable. \"Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain\" (US-9685536). https://patentable.app/patents/US-9685536","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9685536","json":"https://patentable.app/api/llm-context/US-9685536","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:29:30.473Z"}