{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9685537","patent":{"patent_number":"US-9685537","title":"Gate length control for vertical transistors and integration with replacement gate flow","assignee":null,"inventors":[],"filing_date":"2016-09-29T00:00:00.000Z","publication_date":"2017-06-20T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":8,"abstract":"A method of fabricating a vertical transistor is provided, the method including providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate, an impurity layer of n-type or p-type over the semiconductor substrate, a first hard mask layer over the semiconductor layer, a first dielectric layer over the first hard mask layer, a second hard mask layer over the first dielectric layer, a second dielectric layer over the second hard mask layer and a protective layer over the second dielectric layer. The method further includes patterning the second dielectric layer and protective layer, the patterning forming an opening therein, forming a wrap-around spacer on an inner sidewall of the opening, the forming leaving a smaller opening, forming a vertical channel, and setting a gate length of a wrap-around gate by removing an outer portion of the structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Gate length control for vertical transistors and integration with replacement gate flow","description":"A method of fabricating a vertical transistor is provided, the method including providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate, ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9685537","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9685537","citation_suggestion":"Patentable. \"Gate length control for vertical transistors and integration with replacement gate flow\" (US-9685537). https://patentable.app/patents/US-9685537","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9685537","json":"https://patentable.app/api/llm-context/US-9685537","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:04:14.132Z"}