{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9690495","patent":{"patent_number":"US-9690495","title":"Emulating memory mapped I/O for coherent accelerators in error state","assignee":null,"inventors":[],"filing_date":"2015-11-03T00:00:00.000Z","publication_date":"2017-06-27T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"Embodiments disclose techniques for emulating memory mapped I/O (MMIO) for coherent accelerators in an error state. In one embodiment, once an operating system determines that a processor is unable to access a coherent accelerator via a MMIO operation, the operating system deletes one or more page table entries associated with MMIO of one or more hardware contexts of the coherent accelerator. After deleting the page table entries, the operating system can detect a page fault associated with execution of a process by the processor. Upon determining that the page fault was caused by the process attempting to access one of the deleted page table entries while executing a MMIO operation, the operating system emulates the execution of the MMIO operation for the faulting process, giving the process the illusion that its requested MMIO operation was successful."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Emulating memory mapped I/O for coherent accelerators in error state","description":"Embodiments disclose techniques for emulating memory mapped I/O (MMIO) for coherent accelerators in an error state. In one embodiment, once an operating system determines that a processor is unable to","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9690495","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9690495","citation_suggestion":"Patentable. \"Emulating memory mapped I/O for coherent accelerators in error state\" (US-9690495). https://patentable.app/patents/US-9690495","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9690495","json":"https://patentable.app/api/llm-context/US-9690495","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:00:41.794Z"}