{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9690556","patent":{"patent_number":"US-9690556","title":"Code optimization to enable and disable coalescing of memory transactions","assignee":null,"inventors":[],"filing_date":"2016-06-06T00:00:00.000Z","publication_date":"2017-06-27T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions. Based, at least in part, on an analysis of gathered instrumentation information, the processor dynamically modifies continued execution of the plurality of transactions by adding a coalescing instruction that controls, at least in part, a coalescing of one or more outermost transactions of the plurality of transactions."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Code optimization to enable and disable coalescing of memory transactions","description":"A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transacti","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9690556","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9690556","citation_suggestion":"Patentable. \"Code optimization to enable and disable coalescing of memory transactions\" (US-9690556). https://patentable.app/patents/US-9690556","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9690556","json":"https://patentable.app/api/llm-context/US-9690556","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:40:52.794Z"}