{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9690582","patent":{"patent_number":"US-9690582","title":"Instruction and logic for cache-based speculative vectorization","assignee":null,"inventors":[],"filing_date":"2013-12-30T00:00:00.000Z","publication_date":"2017-06-27T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A processor includes a decoder to decode an instruction, a scheduler to schedule the instruction, and an execution unit to execute the instruction. The instruction is to load a memory operation applicable to a quantity of addresses into an execution vector. The execution vector includes a plurality of vector positions for respective addressees. The instruction is further to evaluate, for a given address in the execution vector at a vector position, whether a cache indicates that a previous memory operation was performed at a higher vector position than the vector position of the given address. The instruction is also to determine, based on the evaluation whether the cache indicates that the previous memory operation was performed at a higher vector position than the vector position of the given address, whether the memory operation will cause a memory error."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Instruction and logic for cache-based speculative vectorization","description":"A processor includes a decoder to decode an instruction, a scheduler to schedule the instruction, and an execution unit to execute the instruction. The instruction is to load a memory operation applic","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9690582","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9690582","citation_suggestion":"Patentable. \"Instruction and logic for cache-based speculative vectorization\" (US-9690582). https://patentable.app/patents/US-9690582","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9690582","json":"https://patentable.app/api/llm-context/US-9690582","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:39:07.118Z"}