{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9691484","patent":{"patent_number":"US-9691484","title":"Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate","assignee":null,"inventors":[],"filing_date":"2016-04-04T00:00:00.000Z","publication_date":"2017-06-27T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","H01L"],"num_claims":14,"abstract":"A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate","description":"A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9691484","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9691484","citation_suggestion":"Patentable. \"Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate\" (US-9691484). https://patentable.app/patents/US-9691484","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9691484","json":"https://patentable.app/api/llm-context/US-9691484","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:40:49.667Z"}