{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9696379","patent":{"patent_number":"US-9696379","title":"Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers","assignee":null,"inventors":[],"filing_date":"2016-03-30T00:00:00.000Z","publication_date":"2017-07-04T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":10,"abstract":"A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip includes functional circuitry, and the second chip includes control circuitry for capturing and restoring a microarchitecture state of the functional circuitry of the first chip. The method includes initializing a system state of the semiconductor device and entering a wait state for a state capture triggering event. In response to an occurrence of a state capture triggering event, state data representing a current system state of the functional circuitry on the first chip is captured. The captured state data is transferred to the second chip through a system state I/O (input/output) interface of the second chip under control of the control circuitry on the second chip. A copy of the captured state data is then stored in a memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers","description":"A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip incl","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9696379","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9696379","citation_suggestion":"Patentable. \"Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers\" (US-9696379). https://patentable.app/patents/US-9696379","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9696379","json":"https://patentable.app/api/llm-context/US-9696379","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:18:13.354Z"}